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Customer Success 
Latest Success Stories
By Category  
3Leaf Systems
Design Challenge
Shorten the overall design and verification process time
Incorporate a formal verification strategy into the existing flow to increase the quality of results over simulation

Cadence Solution
Introduced the design team to a formal verification strategy as part of the Assertion-based Verification flow that allowed them to accelerate ramp up and achieve desired results for both quality and efficiency
 Read Full story »
Accent
Design Challenge
Consumer products such as laptops, cell phones, etc., require ever-longer battery life and ever-higher performance, making power management a critical design issue
At 90nm and below, increased leakage can mean that devices consume as much power when they are not in use as when they are being used
Customers require proven low-power solutions, including physical IP
Need a robust design flow that enables correct physical implementation and timing sign off for low-power designs

Cadence Solution
Dynamic-power reductions of 35-40%; leakage reductions of 14-39%
Proved the MSMV flow on a real design, using Cadence technologies, and ARM Artisan IP
Collaborated with both Accent and ARM to develop and test a new multiple-supply, multiple-voltage (MSMV), low-power design methodology
Enhanced several key Cadence technologies to support MSMV methodology
 Read Full story »
Agere Systems
Design Challenge
Adopt a new verification environment to enable hardware/software co-verification
Speed development time for 6-million-gate Link Layer Processor

Cadence Solution
Demonstrated the power of the Cadence Palladium® accelerator/ emulator by bringing up a new verification environment in only two weeks
Success of initial project convinced Agere to choose the Incisive Palladium II system for future designs
 Read Full story»
Anchor Bay
Design Challenge
Larger chips but shorter design cycles
Integrating an entire transceiver supporting multiple standards onto a single SoC

Cadence Solution
Cadence Incisive Xtreme III boosts design team verification productivity with instant "hot swap" among simulation, acceleration, and emulation
 Read Full story»
Bayside Design Inc
Design Challenge
Develop a complete evaluation system for 6.5-Gbps SerDes design, including package, board, FPGA, and software for debug
Complete project in eight weeks

Cadence Solution
Upgraded design environment with Cadence Allegro® system interconnect design platform
 Read Full story »
Celestial Semiconductor
Design Challenge
Convert to a 0.13µm process while increasing the frequency to 220MHz
Minimizing the impact of IR drop and signal integrity
Tape out the chip in a very tight project schedule

Cadence Solution
Cadence® Encounter® digital IC design platform
 Read Full story »
ClearSpeed
Design Challenge
Achieve better compliance measurement of verification processes
Reach coverage goals easier and faster to meet aggressive time-tomarket schedules
Improve project management capabilities

Cadence Solution
The Cadence Compliance Management System provided ClearSpeed a simple, automated path to complete compliance verification
Read Full story »
Cray Inc
Design Challenge
Create a 4-million gate ASIC on a nine-month design schedule to meet critical market window
Integrate legacy components into new design
Find a vendor to address the physical design and complete DFT

Cadence Solution
Partnered with Cray to complete the physical design and address the DFT challenge
 Read Full story »
Epoch Microelectronics
Design Challenge
Larger chips but shorter design cycles
Integrating an entire transceiver supporting multiple standards onto a single SoC

Cadence Solution
Integrated full-chip RF design and simulation methodology
Mixed-signal verification
 Read Full story »
F5 Networks Inc
Design Challenge
Design an ASIC that was approximately four times larger than previous designs in both silicon area and gate count
Apply new methodology to deal with challenges brought on by increased design size and complexity

Cadence Solution
Implemented Cadence Encounter® RTL Compiler global synthesis
 Read Full story »
 
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